Radical Efficiency: New SLICE-CiM Engine Revolutionizes AI Inference in Hardware

Breaking the Memory Wall in Artificial Intelligence

As artificial intelligence (AI) migrates from the cloud to edge devices—such as smartphones, industrial sensors, and wearables—the semiconductor industry faces an existential challenge: power consumption. The traditional computing model, where data constantly travels between the processor and memory, creates what experts call the “memory wall.” This data movement consumes orders of magnitude more energy than the actual computation. To address this, SRAM-based Compute-in-Memory (CiM) technology has emerged as a promising solution, performing calculations directly where the data resides.

However, even the most advanced CiM implementations suffer from hidden inefficiencies in their peripheral logic. This is where the groundbreaking work of Pratham Sharma, Mohd Faisal Khan, and Santosh Kumar Vishvakarma comes in. In their newly published study, the researchers present SLICE-CiM, a selective layer-wise inference control engine that directly attacks the energy waste previously overlooked by technical literature.

The Anatomy of SLICE-CiM: Four Pillars of Innovation

The problem identified by Sharma, Khan, and Vishvakarma lies in three primary peripheral logic inefficiencies: bit-slice over-activation at reduced precision, unnecessary accumulation depth, and idle stalls during precision transitions. To combat these issues, the team developed four synthesizable peripheral blocks that work in harmony.

The first is the Flush-Merge Enable (FME) controller, designed to minimize switching activity. The second is the Confidence-Based Early-Exit (EE) module, which is perhaps the most analytical component of the system. This module allows the hardware to stop processing a neural network layer as soon as a statistical confidence level is reached, saving precious clock cycles. Complementing the system, the Precision Register with Decoder (PR/PD) and the Bit-Serial Cycle Controller (CC) allow the chip to dynamically adjust its operation according to the task’s requirements.

Implemented in a TSMC 65-nm CMOS process at a frequency of 335 MHz, the framework occupies a post-synthesis area of just 1769.760 μm2. Detailed power analysis revealed that the Early-Exit module dominates dynamic power (58.2%), while the wordline generator (WLG) is primarily responsible for area occupancy (58.1%).

Impressive Results and the Future of Deep Tech

The effectiveness of SLICE-CiM was tested using the MobileNetV2 network with the CIFAR-100 dataset. The results are transformative for the hardware sector. The system’s efficiency scaled from 31.35 TOPS/W (Tera Operations Per Second per Watt) in an 8-bit configuration to an impressive 454.91 TOPS/W when operating at 2-bits at 0.8 V. This represents a 13.33x improvement in energy efficiency.

What makes the discovery by Sharma, Khan, and Vishvakarma particularly valuable to the industry is that these gains were achieved without the need to modify standard SRAM memory bitcells or perform complex retraining of AI models. This means the technology can be integrated into existing chip design flows with relative ease.

While the current focus of SLICE-CiM is on Convolutional Neural Network (CNN) workloads that exploit data sparsity, the authors are already pointing toward the next horizon: extending this framework to Transformer architectures, the foundation of modern language models. The practical impact is clear: smarter AI devices that last much longer on a single battery charge, bringing us closer to ubiquitous and truly sustainable computing.

• Scientific Source: SLICE-CiM: Selective Layer-wise Inference Control Engine with Confidence-Based Early Exit for SRAM based Digital Compute-in-Memory — Authors: Pratham Sharma, Mohd Faisal Khan, Santosh Kumar Vishvakarma. Available on arXiv.